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Erlend's avatar
Erlend
Icon for New Contributor rankNew Contributor
5 years ago

Constraining signal on FPGA output

Hi I am currently working on a ADC driver interface and I have come across the following timing requirement for the chip-select signal. My sclk is running at 50MHz, 20ns time period. Notice that bo...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Since you need more time on this. I will put to close pending and you may reopen this in future or simply create new case.