Constraining output enable in TimeQuest for ZBT SRAM

Hi,

I have a zero bus turn around SRAM that is source synchronous, Cypress CY7C1470V33.

I am using a Cyclone IV FPGA.

I have used set_output_delay to constrain the data, address and control signals relative to the clock

to meet the clock to data valid, setup and hold time requirements of the SRAM.

However, I can not figure out how to constrain the output enable for the data pins such that there is no bus contention.

When going from write to a read (falling edge of output enable),

I need a minimum clock to Hi-Z of 1.2 nsec and a maximum of 1.7 nsec.

When going from a read to a write (rising edge of output enable),

I need a minimum clock to lo-Z of 4.5 nsec and a maximum of 6.0 nsec.

Any suggestions would be appreciated.

Thanks,

Jennifer