Honored Contributor
Honored ContributorHi Rysc
I think it is important to explain what have confuse me and properly others when starting to use TQ. So I will try again in another way, please ask or correct me if you think I do not understand it correctly now. From case 3: create_generated_clock -source [get_pins{inst1|altpll_component|auto_generated|pll1|clk[1]}] -name ssync_tx_clk_ext [get_ports {ssync_tx_clk}] When I viewed above clock in TQ waveform I expected it to view the signal as it will appear on the HW pin ssync_tx_clk: so it should view delayed phase compared to the sys_clk_90shift. But TQ does not do that. Instead it view the clock signal named ssync_tx_ext as it is on the outclock input of ddr_tx_clk which is in the same phase as sys_clk_90shift, actually the same phase. So I did not understand how the analyze could be correct and tried to add the delay to the padio manually because I though TQ did not support ripple clocks properly. Finally I realize that TQ moves this clock delay into the data delay as a negative data when displayed in TQ waveform.
