Honored Contributor
Honored ContributorTo be honest, I didn't follow the first part. The latching clock for case 3 should start at the clock coming into the FPGA, through the PLL, global clock tree, any ripple clocks on the path(which would have a generated clock assignment) and finally to the output port driving the clock out(which also has a generated clock on it). I call this final generated_clock *_ext because it is whast is used to clock the external register being driven by our output data ports.
Anyway, it sounds like you have it and our comfortable, I'm just trying to understand the confusion better to see if there's a better way to explain it(or cut it out in carbon).
