Honored Contributor
Honored ContributorHi Rysc,
Forgive me but I have to explain my views on some of your points raised in this post. Apologies for diverting away from original thread but I feel it is useful in any case. --- Quote Start --- set_output_delay says how much delay is outside the device. It's -max and -min values say the same thing, just a range of what that external delay is. --- Quote End --- not correct at all. The equations say: max = tsu + (max data delay – min clk delay) min = - th + ( min data delay – max clk delay) Thus the main theme here is external device requirements, not external delays. The actual external board delays are secondary terms and are given anyway in the equations and they cancel out if equal irrespective of amount of delay leaving tSU/tH as main terms. --- Quote Start --- In trying to convert Th in terms of delays, it gets inverted. --- Quote End --- purely a tool related issue. The constraints were predefined by synopsis and set_output_delay –max refers to how much offset is to be inserted by fpga relative to next latching edge while –min refers to how much offset to be inserted to data relative to current edge. --- Quote Start --- Tsu converts directly, because a device's Tsu is basically saying its data path to the input register is Tsu ns longer than the clock path(that's why you have to have the data there that much earlier. --- Quote End --- Wrong. Device’s tSU spec is only and understandably meant to be at pins. The requirements of internal registers are referred to the pins. tSU is not a delay, it is part of timing window. The register timing window will get shifted at pins if its internal data/clk paths are unequal. tSU stays as tSU in its concept whether referred to pins or directly to registers.
