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Altera_Forum
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14 years ago

Constraining external ripple clocks correctly on external pin (pad_io)

Regarding constraining of external clocks generated by registers. I have now used several days trying to make correct constrains for my external clock generated by a DDR register driven by a P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Just run:

report_timing -setup -npaths 20 -detail full_path -to [get_ports SR_*] -panel_name "s: sr" -file "TQ_setup_sr_out.txt"

report_timing -hold -npaths 20 -detail full_path -to [get_ports SR_*] -panel_name "h: sr" -file "TQ_hold_sr_out.txt"

Then attach the two files.

What are the phases on your two PLLs? They seem strange(clk_0 has a slight negative shift, clk_1 has a +45 degree shift?)