Constraining external ripple clocks correctly on external pin (pad_io)

Hi again

I do not understand how looking at Tco can be wrong. Until some month ago we used the old timing analyser and the datasheet report. Tco, Tsu and Th was our reference to see if timing closed on interfaces to external devices.

I have never found any think wrong in these datasheet reports and they have allways match fairly well with gate level simulations and scope measurements.

If the datasheet report do not match the real world HW, Altera will get complains from 1000's of HW designers, they simply must be correct.