Honored Contributor
Honored ContributorHi Rysc
Sorry for the switch, in my first post I referred to your example because it is the same construct as mine. Your case has the drawing that make thinks easier to understand. But I have not run your example at all. My own design has different names. I switch to use my own design in the second post. Yes I used: derive_pll_clocks -use_net_name which produce the different name syntax. My design names are: DDR Ripple output clock: SR_CLK (TQ name = SR_CLK_EXT) Outputs: SR_A, SR_CE, SR_WE Bidir data SR_DQ CLK_80M is the base clock input pin. I have two PLL clocks, one for SR_CLK output and one for other SR_* outputs. If two abstract I can run go through your example on monday (I am off friday) if you think that is the best way to help me?
