Honored Contributor
Honored ContributorHi Rysc
Thanks for fast respons TQ_analysis.tcl ? I am afraid I do not know what TQ_analysis.tcl is. I have searched both the quartus install directory and the design and not found it I use XP and Q 11.1 My background is HW I do both HW and some FPGA designs. I have done ALtera FPGA design for decades, mostly timing stuff like PLL's and I/O drivers. I am new to TQ, this is only my second desing using TQ, so I properly get somethink upside down. About the hold time, I am not sure I understand what you are saying? The external device has a POSITIVE hold time. Data must be hold valid 0.4nS after the rising clock edge on external device = the FPGA output pins. So should I define it as a positive or negative number in my set_output_delay constrain? As I am not sure about how to make the timing constrains so they match real HW I try to compare the clock phases in TQ with the real world signals. I compare two ways, one with TQ datasheet report Tco so see if the phase diff between the clock input pin and the clock output pin match Tco reported. Second I compare it to the waveforms seen during gate level simulations. When they do not match I think the constrains are wrong. My desing is a little more complex than your example, the pll input clock is the system clock and actually do DDR sampling of the databus when reading the SRAM etc. But lets stick to basic issue here for now. TQ Clocks reports CLK_80M Base 12.500 80.0 MHz 0.000 6.250 phase_locked_loops:pll_inst|Clk_Sram:clk_sram_inst|altpll:altpll_component|_clk0 Generated 6.250 160.0 MHz -0.156 2.969 phase_locked_loops:pll_inst|Clk_Sram:clk_sram_inst|altpll:altpll_component|_clk2 Generated 6.250 160.0 MHz 0.781 3.906 SR_CLK_EXT Generated 6.250 160.0 MHz 6.094 9.219 While TQ Clock to output Times report Maximum SR_CLK CLK_80M 1.402 1.402 Rise SR_CLK CLK_80M 1.402 1.402 Fall Mimimum SR_CLK CLK_80M 0.777 0.777 Rise SR_CLK CLK_80M 0.777 0.777 Fall The gatelevel sim shows tco's close to above. SR_CLK_EXT wan be one period shifted in clock report: I get 6.094 - 6.250ns = -0.156 ns But 6.094 or -0.156 nS is far from what the Tco shows, How can this produce correct results for the external device timing? Second there is only ONE clock report in TQ, but the clocks phase of SR_CLK_EXT must be different for FAST and SLOW. Alternative TQ must modify all the related signals delay or setup with the diff. If the later is the case I do not know how to verify my constrains are correct.
