Honored Contributor
Honored ContributorCan you run the TQ_analysis.tcl file but add the following two lines and attach the output? Just want to understand what you're looking at.
-file "SSYNC_setup.txt" -file "SSYNC_hold.txt" I believe a timing simulation will look differently than static timing analysis. For example, in a timing sim you will have your base clock and the PLL will then phase-shift it 90 degrees. In static timing analysis, it will look like the clock is phase-shifted 90 degrees from the beginning(but will only feed destinations fed by the phase-shifted clock). In the end they're equivalent, but may look different. Also, one important thing to note, your Th of 0.4 becomes a negative external delay. A device with a Th of 0.4 is basically saying its internal data path to the register could be 0.4ns SHORTER than the clock path to the register(and hence you must hold the data externally an extra 0.4ns). Because its shorter, that is a negative delay. So your -min value should have -0.4 as its requirement. The TI 5675A example might help(although that device's Th is 0, so negating or not is kind of a don't care). Anyway, attch the files and I'll take a look.
