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Altera_Forum
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15 years ago

Constraining Clock and Data Lines

Hi everyone. I have a system with an FPGA and a DAC, both fed from the same 400MHz clock source. The FPGA logic and DAC input works at 200MHz (the DAC has internal x2 interpolation, so I provide t...
Altera_Forum's avatar
Altera_Forum
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15 years ago

This is intended for use with the Classic timing analyzer.

Timequest can do a very thorough analysis if you directly feed a PLL output to an IO pin but I personally think it's a hassle to set up (but worth the effort if you can't fit your interface into a single IO bank or using a DDR interface). Using the TFF and the Tco constraints enables you to use the Classic analyzer as well.