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Altera_Forum
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15 years ago

Constraining Clock and Data Lines

Hi everyone. I have a system with an FPGA and a DAC, both fed from the same 400MHz clock source. The FPGA logic and DAC input works at 200MHz (the DAC has internal x2 interpolation, so I provide t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is this solution intended for a TimeQuest constraint, or just a general solution? I thought there would be some easier way in TimeQuest, since you mentioned that TimeQuest was created to handle such problams.