Constraining Clock and Data Lines

Well, let's try to keep things simple then.

First of all, things are easiest if the whole DAC interface is located within 1 IO bank. In that case you should give all the pins some ridiculous Tco constraint (0.5ns or so). Do a fit, see what the fitter could actually manage, and update the Tco for the DAC data pins to 0.5ns more than the results you achieved. This gives you predictable data IO timing for the data pins.

Now, of course you realize that a clock is simply a signal too. Since you have a 400MHz clock available, simply create second 400MHz output from the PLL that handles the 400MHz clock and make it drive a toggle-flipflop in your HDL of choice. Assign the output of the TFF to your DAC's data clock pin. Again, set its Tco to something ridiculous, do a fit, and update the Tco to what is achievable plus 0.5ns. This gives you reliable IO timing for the clock output.

What you can now do is adjust the phase shift of the clock toggling the TFF to match the clock/data relationship required by your DAC.

From the second fit you have obtained the phase relationship between the data and clock pins (which is the difference in Tco time between the clock and data pins). This should give you enough room to play with.

Let me know if I'm unclear at some point.

Best regards,

Ben