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Altera_Forum
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15 years ago

Constraining Clock and Data Lines

Hi everyone. I have a system with an FPGA and a DAC, both fed from the same 400MHz clock source. The FPGA logic and DAC input works at 200MHz (the DAC has internal x2 interpolation, so I provide t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for the reply.

I'm using the Stratix III 260 device, so I have 4 PLLs, one of which is dedicated to the 400MHz input. I naturally thought of what you considered, inspecting the timing of every fit and selecting an appropriate phase for a PLL output. Obviously this is a horrible solution :) I was hoping to get around that.

I hadn't got used to the TimeQuest analyzer yet so I'm still sticking to the old classic one. How would you go about constraining it in the TimeQuest analyzer?

If you need any specific info, I'll be delighted to share.