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Altera_Forum
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15 years ago

Constraining Clock and Data Lines

Hi everyone. I have a system with an FPGA and a DAC, both fed from the same 400MHz clock source. The FPGA logic and DAC input works at 200MHz (the DAC has internal x2 interpolation, so I provide t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Can't think of any Classic timing analyzer setting that does this - this is a typical source-synchronous scenario for which timeQuest was created.

Depending on what FPGA you have and how many PLL outputs you have left, there _is_ a fairly simple solution for this, but you'll have to manually inspect timing every time you do a fit. If you give me a bit more info I can probably help you do what you need to.

Best regards,

Ben