Constrained clock appears as unconstrained input

Mysterious !

In very similar design I did before there is no such issues.

Short resume:

TimeQuest analysis generates unconstrained path error on output dram_clk.

This port delivers clock to external SDRAM chip and it's constrained with the following instruction:

create_generated_clock -name clk_dram -source [get_pins {u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {dram_clk}]

Here is TimeQuest diagnostic, related to this DRAM_CLK port (setup analysis):

unconstrained output ports:

DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

unconstrained output port paths:

From

To

From Clocks

u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk

DRAM_CLK

u0|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]

The same messages are present in hold analysis.

Probably I've been mistaken with create_generate_clock instruction ?

Thanks.