Constrained clock appears as unconstrained input

I've tried with zero delay buffer: with this option PLL generates an additional output, that should be connected somewhere. I didn't understand this option and finally selected "normal" option.

Also I din't increase PLL-generated clocks and didn't introduce phase shift.

With this concept the problem didn't completely disappear - while with base clock (i.e. CLOCK_50), it's OK, DRAM_CLK still appears as unconstrained output.

Here is fragment of Qsys:

https://www.alteraforum.com/forum/attachment.php?attachmentid=14124

And here is .sdc file:

#**************************************************************
#  This .sdc file is created by Terasic Tool.
#  Users are recommended to modify this file to match users logic.
# **************************************************************
# **************************************************************
#  Create Clock
# **************************************************************
create_clock -period 20.0 -name clk CLOCK_50
derive_pll_clocks
derive_clock_uncertainty
#  for enhancing USB BlasterII to be reliable, 25MHz
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_output_delay -clock altera_reserved_tck 3 
# **************************************************************
#  Create Generated Clock
# **************************************************************
#  **** next stetement modified by GooGooCluster ***
# create_generated_clock -name clk_dram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name clk_dram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] 
# **************************************************************
#  Set Input Delay
# **************************************************************
#  Board Delay (Data) + Propagation Delay - Board Delay (Clock)
set_input_delay -max -clock clk_dram -0.048 
set_input_delay -min -clock clk_dram -0.057 
# **************************************************************
#  Set Output Delay
# **************************************************************
#  max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
#  min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
set_output_delay -max -clock clk_dram 1.452  
set_output_delay -min -clock clk_dram -0.857 
set_output_delay -max -clock clk_dram 1.531 
set_output_delay -min -clock clk_dram -0.805 
set_output_delay -max -clock clk_dram 1.533  
set_output_delay -min -clock clk_dram -0.805 
set_output_delay -max -clock clk_dram 1.510  
set_output_delay -min -clock clk_dram -0.800 
set_output_delay -max -clock clk_dram 1.520  
set_output_delay -min -clock clk_dram -0.780 
set_output_delay -max -clock clk_dram 1.5000  
set_output_delay -min -clock clk_dram -0.800 
set_output_delay -max -clock clk_dram 1.545 
set_output_delay -min -clock clk_dram -0.755 
set_output_delay -max -clock clk_dram 1.496  
set_output_delay -min -clock clk_dram -0.804 
set_output_delay -max -clock clk_dram 1.508  
set_output_delay -min -clock clk_dram -0.792 
# **************************************************************
#  Set Clock Groups
# **************************************************************
# **************************************************************
#  Set False Path
# **************************************************************
set_false_path -from 
set_false_path -from 
set_false_path -from * -to 
set_false_path -from * -to 

Any comments ?