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Honored Contributor
Honored ContributorConstrained clock appears as unconstrained input
Hello, I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I loo...
Altera_ForumHonored Contributor
Honored ContributorFinally I've found the source of problem.
It's caused by assign dram_clk = clock_50 assignment. When I comment it, timing analysis passes without reporting unconstrained input/output. But I still need to "redirect" system clock clock_50 to dram_clk to clock external SDRAM chip. I've tried buf(dram_clk, clock_50) instead of assign dram_clk = clock_50 ... and problem reappeared. Any suggestions ?
