Constrained clock appears as unconstrained input

Thank you GooGooCluster,

I've just tried your suggestions.

Unfortunately the result is the same - timing analysis reports two unconstrained ports - clock_50 and dram_clk.

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If I understand you correctly, your PLD receives the reference clock at the CLOCK_50 pin, and internally routes that pin to the DRAM_CLK output pin; all external logic receives its clock from the PLD's DRAM_CLK pin.

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Yes, the FPGA (Cyclon V) receives 50MHz clock (generated on the board) at clock_50.

Then this clock is "redirected" (assign DRAM_CLK = CLOCK_50) to clock external SDRAM chip.

Concerning other SDRAM staff (i.e. DRAM_***), all these ports are clocked by the clock, derived from main system clock (i.e. CLOCK_50), as these interface ports are "created" by inserting the "SDRAM controller IP" in Qsys.

I used a virtual clock for creating input/output delays for SDRAM staff, which you suggested to comment (i.e.# create_clock -period 20.0 -name clk_dram) because in all manuals that I'v seen until now it's this "mysterious object", named virtual clock, that is used for creating input/output delays. In the same time in all these manuals, the clock for external module is generated outside FPGA, whereas in my case (and I think in majority cases, it's FPGA, that delivers clock for external module).

So, I consider your suggestion as quite reasonable, but unfortunately it didn't help ... probably due to some option improperly set somewhere.

Regards.