Constrained clock appears as unconstrained input

Hi,

If I understand you correctly, your PLD receives the reference clock at the CLOCK_50 pin, and internally routes that pin to the DRAM_CLK output pin; all external logic receives its clock from the PLD's DRAM_CLK pin.

These changes should fix your warnings:

...
create_clock -period 20.0 -name clk 
# create_clock -period 20.0 -name clk_dram
...
create_generated_clock -name clk_dram -source  
...

The first statement defines a logical clock named "clk", which comes from the pin "CLOCK_50". You already had that, but I'm not sure if it really works without "get_ports()", so I added that.

The second statement is, as far as I understand it, wrong, so I commented it out.

The third statement defines another logical clock, named "clk_dram", which is basically the same as "clk", but measured with pin "DRAM_CLK" as a reference. I fixed the name of the clock that it generates.

Below that, there should be all your set_xyz_delay statements, where you already use the clock name "clk_dram".

Hope that helps.

- GooGooCluster