Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Constant declaraion with calculation in VHDL

Hi, I have some constants declared in VHDL with the "third one" being dependent on the value of the other two. As my experience is, that I normally forget to change the "third" when changing eithe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

well this is part of a VHDL File "using" a Cyclone IV EPC4CE15 by 95%. The code is neither handy nor am I allowed to post it here as whole. I agree just posting snipets makes things not easier to investigate or explain.

Regarding the libraries used - this is a "relict" of the first lines being written somewhat 20 years ago. While the content (the "working code") changed over the years the header of the VHDL file was copied each time...

I played around a little with the suggested nummeric_std - this requires modification of the library declaration and to the code, does it?

(i.e. SIGNAL xyz: STD_LOGIC_VECTOR(...) changes to either SIGNAL xyz: SIGNED () or UNSIGNED (), CONV_STD_LOGIC_VECTOR changes to TO_SIGNED () or TO_UNSIGNED ()...)

While this is a lot of work, this might be a point to review more detailled the complete code and get rid of all those "historical" constructs.

Carlhermann