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Altera_Forum
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13 years ago

Constant declaraion with calculation in VHDL

Hi, I have some constants declared in VHDL with the "third one" being dependent on the value of the other two. As my experience is, that I normally forget to change the "third" when changing eithe...
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Altera_Forum
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13 years ago

FvM; Yes, I would agree it is caused by the ambiguities of the ieee std_logic_signed library versus using numeric_std. In my earlier post I alluded to this; and in a derived calculation each data type must be explicitly declared, i.e. :

derived_constant : std_logic_vector(15 downto 0) := to_unsigned(2047,16) - constant_1 - constant_2

where ieee.numeric_std.all is declared versus signed or unsigned libraries.

James