Constant declaraion with calculation in VHDL

To avoid wrong conclusions of mine, can you post a code example using the said constants that shows the wrong behaviour.

I guess, that the problem is caused by ambiguities of the Synopsys STD_LOGIC_SIGNED library. But it can only show in comparisons, there's no actual difference between signed or unsigned in add and sub operations. If you add X"7FF" and X"100", the result is always X"8FF", either if the results represents a signed or unsigned quantity.

I asked about Quartus versions, because I tried to understand why I never faced a similar problem. But now I assume, it's due to the fact that I never use the weakly typed STD_LOGIC_XXX libraries.