Constant declaraion with calculation in VHDL

Hi all,

well I'm currently working with Quartus II, v12.0, while the code was originally written and compiled with v11.1, SP2. I did not yet compiled with any older version to confirm this to be related to v12.0.

The used libraries are

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_SIGNED.ALL;

The intention is that I have a control loop which has a vector "RAG" as output value, which is 12Bit, signed. This vector must be limited to the symmetric window given by RAG_max to RAG_min (with RAG_min being -RAG_max) to generate the correct output by the PWM module connected (the minimum Duty Cycle and Crossover between the PWM output are limited by connected hardware).

RAG_max as the positive limit is +max-1 for a 12Bit signed vector (being 2047-1=2046) reduced by PWM_DC_min and PWM_Crossover, i.e. +2046-120-6=1921 or x"780" in 12Bit Hex, signed representation (x"7FE"-x"78"-x"6"). Similarly RAG_min should be the max negative value for 12 Bit signed increased by PWM_DC_min and PWM_Crossover. (RAG_min = -RAG_max would be equivalent equation).

Regarding the different version of Quartus, I would have to recompile the code using 11.1SP2 (for any older version I would have to reinstall these).