Constant declaraion with calculation in VHDL

Actually, I think the issue may be not explicitly declaring the 2047 inside the third type as unsigned. For example:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;  
use ieee.math_real.all;
entity calibrate is
    generic (regSize : integer := 16);
     port(
         MCLK     : in  std_logic;
         HRST     : in  std_logic;
         ENABLE   : in  std_logic;
         START    : in  std_logic;
         Xin      : in  std_logic_vector(regSize-1 downto 0);
         Xout     : out std_logic_vector(regSize-1 downto 0);
         DONE     : out std_logic
         );
end calibrate;
architecture rtl of calibrate is 
constant Nsamples  :  integer := 4;
constant Z         :  integer := integer(ROUND(LOG2(1.0*real(Nsamples))));
constant N         :  integer := integer(Z) + regSize;
type accumType is record
    val : signed(N-1 downto 0);
end record;
signal accum : accumType;
type counterType is record
    start : std_logic;
    done  : std_logic;
    val   : integer range 0 to Nsamples-1;
end record;
signal counter : counterType;
signal load    : std_logic;     
signal doneDly : std_logic;
begin
/*--------------------------------------
   Accumulate offset
--------------------------------------*/
FX: process(all) begin
    if HRST then
        accum.val <= (others => '0');
    elsif rising_edge(MCLK) then
        if load then
            accum.val <= (others => '0');
        elsif START and not(counter.done) then
            accum.val <= accum.val + resize(signed(Xin),N);
        end if;
    end if;
end process FX;    
process(all) begin
    if HRST then
        Xout <= (others => '0');
    elsif rising_edge(MCLK) then
        if counter.done then
            Xout <= std_logic_vector(accum.val(N-1 downto Z)) ;
        end if;
    end if;
end process;
Uedge1 : entity work.POS_EDGE(rtl)
    port map(
        CLK     => MCLK,
        HRST     => HRST,
        X         => counter.done,
        Y         => doneDly
    );
    
Udff1 : entity work.D_FF(rtl)
    port map(
        CLK     => MCLK,
        HRST     => HRST,
        X         => doneDly,
        Y         => DONE
    );    
/*--------------------------------------
   Edge detect enable mode
--------------------------------------*/
Uedge : entity work.POS_EDGE(RTL)
    port map(
        CLK     => MCLK,
        HRST     => HRST,
        X         => ENABLE,
        Y         => load
    );
/*-------------------------------------------
           Count the number of samples
---------------------------------------------*/
counter.start <= START;
process(all) begin
    if HRST then
        counter.val  <= 0;
        counter.done <= '0';
    elsif rising_edge(MCLK) then
        if load then
            counter.val <= Nsamples-1;
            counter.done <= '0';
        elsif counter.start then
            if counter.val > 0  then
                 counter.val <= counter.val - 1;
                counter.done <= '0';
            else
                counter.done <= '1';
            end if;
        end if;
    end if;
end process;
end rtl;