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Altera_Forum
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13 years ago

Constant declaraion with calculation in VHDL

Hi, I have some constants declared in VHDL with the "third one" being dependent on the value of the other two. As my experience is, that I normally forget to change the "third" when changing eithe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Which libraries are you using? I assume that you use one or more of the SYNOPSYS libraries. In this case I suggest to use the numeric_std library instead and try the following code.

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Yes the code in the initial post is apparently using legacy std_logic_arith and std_logic_unsigned, but I was'n able to reproduce the problem at first attempt with these libraries.