Constant declaraion with calculation in VHDL

Which libraries are you using? I assume that you use one or more of the SYNOPSYS libraries. In this case I suggest to use the numeric_std library instead and try the following code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY constant_math IS
END ENTITY constant_math;
ARCHITECTURE rtl OF constant_math IS
    CONSTANT PWM_DC_min    : std_logic_vector(11 DOWNTO 0) := std_logic_vector(to_unsigned(120, 12));
    CONSTANT PWM_Crossover : std_logic_vector(11 DOWNTO 0) := std_logic_vector(to_unsigned(6, 12));
    CONSTANT RAG_max       : std_logic_vector(11 DOWNTO 0) := std_logic_vector(2046 - unsigned(PWM_DC_min) - unsigned(PWM_Crossover));
    CONSTANT RAG_min       : std_logic_vector(11 DOWNTO 0) := std_logic_vector(2050 + unsigned(PWM_DC_min) + unsigned(PWM_Crossover));
    
BEGIN  -- ARCHITECTURE rtl
END ARCHITECTURE rtl;