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Altera_Forum
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13 years ago

Constant declaraion with calculation in VHDL

Hi, I have some constants declared in VHDL with the "third one" being dependent on the value of the other two. As my experience is, that I normally forget to change the "third" when changing eithe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

My suggestion is to put these within the main architecture as signals, completely determined by constants: 


RAG_max <= x"7FE"-PWM_DC_min-PWM_Crossover;
RAG_min <= x"802"+PWM_DC_min+PWM_Crossover;
I have had similar issues in the past and have resorted to this paradigm of VHDL implementation in Quartus. -James