Connecting DDR3 on ArriaII GX Development Kit

Using Quartus II 12.0. Same error with Stratix IV / DDR2 Controller

Project is from terasic QSYS 11.0 DDR2 Example. I only added a PCIe IP Core.

The DDR2 Controller has an 50 MHz(OSC_50_Bank3) input clock, no PLL. :(

Found on: quartushelp[.]atlera[.]com

ACTION: Use the on-chip phase-locked loop (PLL) as the input clock source to the memory block.

Strange. The example from terasic (DE4_DDR2_UniPHY) does not use a PLL as an input clock and it works without critical errors. why?

Edit:

Still doesn't work with PLL. :confused: