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treble99's avatar
treble99
Icon for New Contributor rankNew Contributor
3 years ago

Connecting Avalon Streaming signals to Signal Tap Logic Analyzer

Hello, I am trying to simulate PCIe_DDR4 example provided for Terasic DE5a-NET DD4(Intel Arria 10 GX FPGA (10AX115N2F45E1SG)). I have made a modification to the project. After opening it in Quart...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Don't run Signal Tap as an IP. That's not a recommended flow, especially with Platform Designer since you can't manually instantiate and select signals to tap as you have found. Remove that from PD, compile the design (or just run analysis & elaboration), create a new .stp file, and tap signals directly from the Node List (via the Node Finder) in Signal Tap. Recompile and you're good to go.