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Altera_Forum
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14 years ago

Confusion about Source-Synchronous constraints

Hi, everyone: I use FPGA to capture the output data of ADC. The ADC output timing is as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=3894 In Altera's "AN 433 ...
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Altera_Forum
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14 years ago

Thank you for your quick reply, sir.

However, I have something to be further clarified:

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I don't know from where you got your example.

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It's from "Quartus II 10.1 Handbook, Vol. 3, Chap 7, Page 5, Example 7–6" and I am confused about the set_output_delay, too. So I want to make sure what's going on with the situation.

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You need to set input delay at the fpga according to tCO of ADC which equals half UI if ADC is centre aligned.

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I just began to use altera's device and develop tools. Could you please show me the meaning of "UI"? Thanks.

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What matters is that fpga knows relation of ADC data to clock at fpga pins.

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This really helps me. Thank you very much.