Confusion about Source-Synchronous constraints

For ADC you need to set input delay.

The virtual clock is used for input delays, not output delay, I don't know from where you got your example.

If your ADC data is centre aligned and stays so at FPGA then you don't need to rotate a clock that is already rotated for you.

You need to set input delay at the fpga according to tCO of ADC which equals half UI if ADC is centre aligned.

You can use virtual clock if you want to tell fpga the about board delays but is not necessary. What matters is that fpga knows relation of ADC data to clock at fpga pins.