Confused by timequest timing analyser

Your setup relationship is the requirement between the two clocks. (In this case it is always 10ns). Note that I/O requirements get reported just like internal paths.

Let's look at your first set_input_delay constraint. Remember to think of set_input_delay like a circuit description. It says there is an external register driving data into data*. That register is clocked by ext_clk and it takes between 1-4ns to get to the data* port. Since the external clock is the same as the internal clock, they have a 10ns relationship. (Draw the clock waveforms, and you'll see that when clk_ext launches data, it needs to get to clk within 10ns.) Now 4ns of that is used externally, so your leaving 6ns for the FPGA delay, i.e. the FPGA's data delay - clock delay to the internal register must be less than 6ns.

Remember that this is hypothetical. In a real design, your multiplier is driven by something. So if the external device had a Tco of 3.5ns, and the board delay was 0.5ns, then your external delay is 4ns. That makes sense since you've really described what's going on outside the FPGA. I believe you're case is made up, and so it's confusing how 4ns is the value you came up with.

On the hold side, look at your clock waveforms. The data sent from clk_ext must not get to clk in less than 0ns. So that's your hold relationship. Since the external delay is 1ns, the only way the FPGA could fail timing is if it's delay was -1ns, i.e. it's data delay - clock delay to the register was -1ns.

Finally, on your output delays you seem to have switched max and min values, which I don't get. Your -max should really be larger than your -min. If your max was 4ns, then you'd do the same thing. You have a 10ns setup relationship, 4ns is used external, and hence the FPGA must get it's data out in 6ns(kind of like a 6ns Tco).