Confused by timequest timing analyser

Well i am still really confused how to add constraints to achieve a particular goal, i have read many posts on altera forum discussing the constraints assignments ( and gone through the training + documents ) to reach design goals but still find it a bit obscure.

1. I think as a beginner i would like to see how a design is constrained using a simple example and i hope that others will help me out.

2. My objective in this case is to design a simple multiplier to work

(a) at a specific frequency e.g 100Mhz

(b) find out the maximum frequency of operation of the multiplier

3. My simple design in verilog is as follows,

module mul1( clk,
                reset,
                dataa,
                datab,
                start,
		done,
                result);
   input             clk;
   input             reset;
   input   dataa;
   input   datab;
   input             start;
   output            done;
   output  result;
   
   reg  done;
   reg   result;
	
	always @(posedge clk) begin
		if (reset) begin
			result <= 32'b0;
			done <= 0;
		end
		else begin
			if (start) begin
				result <= dataa * datab;
				done <= 1;    // done asserted when result ready
			end
			else begin
				if (done) begin
					done <=0; 
				end
			end
		end 
	end 
endmodule

4. The code can be synthesized using DSP's or LUT's but in this case let us assume that we need the fastest implementation so we opt for the DSP based multipliers.

5. I think single cycle constraints are the easiest so we should constrain using them first (I DONT THINK MUTI CYCLE CONSTRAINTS ARE APPLICABLE TO THIS PARTICULAR DESIGN ? )

6. Assuming that we want to see if the design will work at 100Mhz, i have made a sample sdc file

create_clock -period 10.000 -name real_clock 
create_clock -name ext_clk -period 10.0 
set_input_delay -clock ext_clk -max 4.0 
set_input_delay -clock ext_clk -min 1.0 
set_input_delay -clock ext_clk -max 4.0 
set_input_delay -clock ext_clk -min 1.0 
set_input_delay -clock ext_clk -max 4.0 
set_input_delay -clock ext_clk -min 1.0 
set_output_delay -clock ext_clk  -min 4.0 
set_output_delay -clock ext_clk  -max 1.0 
set_output_delay -clock ext_clk  -min 4.0 
set_output_delay -clock ext_clk  -max 1.0 

7. I have taken the 10ns period from the 100Mhz requirement but have put the input and output delay values at random ? , i do not understand the strategy for choosing these values?.

8. A sample line from the worst-case timing path for set up is as follows

slack from Node to node launch clk latch clk relationship clk_skew

------ ------------- ---------- ------------ ---------- -------------- ---------

-3.609 dataa[1] result[62]~reg0 ext_clk real_clock 10.000 3.457

data delay

----------

13.084

9. In the above design i dont understand why timequest takes the ext_clk as the launch edge clk and real_clk as the latch edge clk ? , and what does relationship column mean ?

10. TO ask something more fundamental , is it correct to translate our frequency spec to input / output delays ?

I hope you guys can help me out

Thanks

Silva