Confused by timequest timing analyser

The uTsu must be a negative number. Note that these are not always pure numbers. For example, they register might theoretically have a uTsu and uTh, but that's always in relation to the clock coming into it. There's no black-and-white point where that clock comes in, so maybe they're rolling more or less of the register clock delay into that uTsu/uTh. I've seen some stuff like that done over the years, and though they try to avoid it, if the final answer is correct that's the important thing.

(But yes, in theory the uTsu should shorten your data required time, making it harder to meet setup timing. Again, in practice may deviate a little from in theory...). I tend to concentrate on the numbers I can control, clock relationships, levels of logic and routing delays.