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John-Monahan's avatar
John-Monahan
Icon for New Contributor rankNew Contributor
7 years ago

Configuring the Quartus IP library "RS232 UART, CLK signal

I am trying to add the Quartus IP library "RS232 UART" into a .bdf file. Seems to load fine but during the "Generate" I get an error "The input clock frequency must be known at generation time." How...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

In Quartus Prime (V18) Go to Tools -> Platform Designer.

Seems to load fine but during the "Generate" I get an error "The input clock frequency must be known at generation time."

Check the below KDB link,

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/error--rs232_0--the-input-clock-frequency-must-be-known-at-gener.html

For Baud rate setting refer the below link,

ftp://ftp.altera.com/up/pub/Intel_Material/16.1/University_Program_IP_Cores/Communication/RS232.pdf

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)