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Altera_Forum
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7 years ago

Configuring Arria V using MAX II and flash

Hi everyone, I am trying to configure Arria V using Max ii CPLD and on board flash using PFL IP. My question is 1) when I try to generate the pof file for the CPLD, it asks me for the configu...
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Altera_Forum
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7 years ago

AN478 discusses using a parallel FLASH device in AP (Active Parallel) programming mode - without a CPLD. In this programming method the target FPGA generates the control signals for the parallel FLASH device that's connected directly to it.

If you want to program an FPGA using a CPLD to control the FLASH memory then you need to use FPP (Fast Passive Parallel) mode, for which you will not need the PFL IP.

Refer to the relevant section on page 8-15 of the 'arria v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/arria-v/av_5v2.pdf)'. You will need to generate a raw binary file or similar (not a .pof) to program into your parallel FLASH.

Cheers,

Alex