concurrent host and device memory accesses

If your board supports host channels (which have been supported in Altera's reference board since v17.1), you can use that. If not, considering the fact that OpenCL only guarantees global memory consistency after full kernel execution, there is no way to know when the data in the FPGA external memory is valid during kernel execution to read it on the host. However, you might be able to get it to work by having two buffers on the FPGA external memory, and a separate kernel writing to each. In this case, you will first write the processed data to buffer A, switch to buffer B while the host is reading from buffer A, then switch back to buffer A when the host is reading from buffer B, and so on. Essentially, double-buffering. Though this will not guarantee uninterrupted processing and hence, you will need a back pressure mechanism for the network connection (there will never be any guarantee for uninterrupted processing, even with host channels; hence, you will need back pressure anyway).