Altera_Forum
Honored Contributor
13 years agoComponent Instantiations in VHDL
Hi All,
I am relatively new to VHDL and I'm trying to implement the following actions for the related ctrl strings: --ADD when ctrl="000" else --SUB when ctrl="001" else ALUOUT <= ABUS and BBUS when ctrl="010" else ALUOUT <= ABUS or BBUS when ctrl="011" else ALUOUT <= ABUS xor BBUS when ctrl="100" else ALUOUT <= not ABUS when ctrl="101" else ALUOUT <= ABUS when ctrl="110" My problem is that I already have an adder designed in a verilog module which I am calling using component instantiation and the principle "A-B=A+(not B) + 1" for the Subtraction operation. The two component instantiations are as below: u1: NBitAdder port map(Aalu=>ABUS, Balu=>BBUS, c=>'0', sumA=>ALUOUT, carryA=>cout); u2: NBitAdder port map(Aalu=>ABUS, Balu=>not BBUS, c=>'0', sumA=>ALUOUT, carryA=>cout); But how can I implement only 1 of these depending on the ctrl inputs?? From what I understand an instantiation cannot be used within the WHEN process. Any help would be much appreciated. Thanks in advance.