Component Instantiations in VHDL

Your mux structure in VHDL should be a little different. Try:

--ADD when ctrl="000" else
--SUB when ctrl="001" else
ALUOUT <= (ABUS and BBUS) when ctrl="010" else
          (ABUS or BBUS) when ctrl="011" else
          (ABUS xor BBUS) when ctrl="100" else
          (not ABUS) when ctrl="101" else
          (ABUS); -- when ctrl="110"

Component instantiations need to be done outside of process statements in VHDL. You will need to create signals to connect to the two outputs and mux them appropriately. Something like the following:

u1: NBitAdder 
  port map
  (
    Aalu => ABUS, 
    Balu => BBUS, 
    c => '0', 
    sumA => u1_sumA_out, --ALUOUT,
    carryA => u1_carryA_out --cout
  );
u2: NBitAdder 
  port map
  (
    Aalu => ABUS, 
    Balu => not BBUS, 
    c => '0', 
    sumA => u2_sumA_out, --ALUOUT, 
    carryA => u2_carryA_out --cout
  );
ALUOUT <= u1_sumA_out WHEN (control = '1') ELSE  u2_carryA_out;
cout <= u1_carryA_out WHEN (control = '1') ELSE u2_carryA_out;