component alt_dspbuilder_DFFEALTR

Hi

I have problem with this component alt_dspbuilder_DFFEALTR from altera library. When I use it the Quartus write me Error (12006): Node instance "m" instantiates undefined entity "alt_dspbuilder_DFFEALTR" and I have no idea how to solve this problem.

Here is my code:

library IEEE;

LIBRARY altera;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

USE altera.alt_dspbuilder_package.all;

entity pokus is

port(

clk: in std_logic;

enable: in std_logic;

input1: in std_logic_vector (3 downto 0);

output1: out std_logic_vector (3 downto 0);

input2: in std_logic_vector (8 downto 0);

output: out std_logic_vector (8 downto 0));

end pokus;

architecture pokuskod of pokus is

signal nulovy: std_logic_vector(8 downto 0) := "0000" & "00000";

signal helpvector: std_logic_vector(8 downto 0);

component alt_dspbuilder_DFFEALTR

GENERIC

(

width : NATURAL := 9);

PORT

(

d : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);

clock : IN STD_LOGIC;

ena : IN STD_LOGIC;

prn : IN STD_LOGIC;

clrn : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0)

);

END component;

begin

m: alt_dspbuilder_DFFEALTR generic map(9)

port map (nulovy(8 downto 4) & input1,clk,enable,'1','1',helpvector);

output1 <= helpvector(3 downto 0);

end pokuskod;

Sorry If I have stupid question, but I am a newer in VHDL and I didn't find anything about this.

Martin