Complex floating-point sequential logic in Verilog

I know next to nothing about graphics, so I don't have much of a clue about the complexity of your undertaking.

That said, the simpler FP megafunctions are already fully pipelined, weather you want it or not. All you have to do is take advantage of that. And in some ways, it should lead to a "simpler" design with less complex state machines.

I'm not sure about more complex ones, such as division and multiply+accumulate.

Quite honestly, I don't actually remember any literature that deals with pipelining and resource scheduling. Although I'm pretty sure there oughta be a few books that do, this is, pretty much, digital design 201 and I learnt most of it from teachers' notes.