Complex floating-point sequential logic in Verilog

Some of the FP functions (at least the simpler ones such as add/sub and mult) are fully pipelined. This means that you can provide them with a new pair of operands each clock cycle and you'll get a new result each clock cycle, with a given delay.

This is, I think, not true for more complex functions such as division (but don't take my word for it).

A calculation such as "(vertX_pos_y - vertA_pos_y) / 240" could easily be pipelined, by replacing "/240" with "*.00416666666666666666".

Depending on your needs, pipelining may be feasisble and may contribute to simplify your state machine.

Otherwise.. you are correct, you need a state machine.

On another note, have you considered fixed point instead of floating point?

It woudl require less resources and less cycles -- which could also simplify your state machine.