compiler can't fit design despite 1st stage compile reporting low utilization

The estimated resource utilization reported after the first stage of compilation is based on Altera's OpenCL model (and not even post-synthesis area utilization) and on Arria 10 I have encountered cases where logic and memory utilization were even 50% off. Modelling area utilization is not easy when the design has not been synthesized, even for Altera, so such discrepancies are expected. Unfortunately there is no way other than full placement and routing to get accurate resource utilization.