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Can you post the code, or a code example showing the same behaviour?
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The part of code which causes the problem is the instantiation of the altsyncram component:
1. This is the original instantiation which works for Quartus but not for Modelsim:
if_single_clock:
IF CLOCK_MODE_ID = SINGLE_CLK_ID GENERATE
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => REG_B_CLK,
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "BYPASS",
init_file => INIT_FILE,
intended_device_family => DEVICE_FAMILY,
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => MEM_OP_MODE,
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => RAM_BLOCK_TYPE,
rdcontrol_reg_b => REG_B_CLK,
widthad_a => fcn_max(fcn_log2_ceil(NUM_WORDS),1),
widthad_b => fcn_max(fcn_log2_ceil(NUM_WORDS),1),
width_a => DATA_WIDTH,
width_b => DATA_WIDTH,
width_byteena_a => 1,
read_during_write_mode_mixed_ports => RD_WR_MIX_PORTS
)
PORT MAP (
wren_a => wren,
clock0 => wrclock,
clocken0 => wrclocken,
clock1 => open,
clocken1 => open,
address_a => wraddress,
address_b => rdaddress,
rden_b => rden,
data_a => wrdata,
q_b => sub_wire0
);
END GENERATE if_single_clock;
2. Changing the PORT MAP to:
PORT MAP (
wren_a => wren,
clock0 => wrclock,
clocken0 => wrclocken,
clock1 => '0', -- or clock1_i
clocken1 => '0', -- or clocken1_i
address_a => wraddress,
address_b => rdaddress,
rden_b => rden,
data_a => wrdata,
q_b => sub_wire0
);
Makes it compile for Modelsim but not in Quartus anymore.
* Component definition (in case this helps) is:
COMPONENT altsyncram
GENERIC (
address_aclr_b: string;
address_reg_b: string;
clock_enable_input_a: string;
clock_enable_input_b: string;
clock_enable_output_b: string;
init_file: string;
intended_device_family: string;
lpm_type: string;
numwords_a: natural;
numwords_b: natural;
operation_mode: string;
outdata_aclr_b: string;
outdata_reg_b: string;
power_up_uninitialized: string;
ram_block_type: string;
rdcontrol_reg_b: string;
widthad_a: natural;
widthad_b: natural;
width_a: natural;
width_b: natural;
width_byteena_a: natural;
read_during_write_mode_mixed_ports: string
);
PORT (
wren_a : IN std_logic;
clock0 : IN std_logic;
clocken0 : IN std_logic;
clock1 : IN std_logic;
clocken1 : IN std_logic;
address_a : IN std_logic_vector (fcn_log2_ceil(NUM_WORDS)-1 downto 0);
address_b : IN std_logic_vector (fcn_log2_ceil(NUM_WORDS)-1 downto 0);
rden_b : IN std_logic;
q_b : OUT std_logic_vector (DATA_WIDTH-1 downto 0);
data_a : IN std_logic_vector (DATA_WIDTH-1 downto 0)
);
END COMPONENT;
We cannot remove clock1 and clocken1 from the component definition because they are used in the cases CLOCK_MODE_ID = LEGACY_CLK_ID or CLOCK_MODE_ID = DUAL_CLK_ID
Honored Contributor
