Compilation Dependent Behavior

I wanted to thank everyone for their help and let everyone know that I have solved the problem!

For anyone with similar problems, I suggest they take the following steps:

1) Run the Timing Advisor from the Quartus Advisor menu.

2) Verify that their logic is correct.

3) If they encounter compilation dependent behavior, attempt to use Logic Locked Regions.

A good approach at using Logic Locked Regions seems to be as follows:

A. Assign a logic locked region to the top-level "device" you are having issues with.

B. Check the Chip Planner to see where the fitter placed the "floating" region. This means that the region can be re-located between compilation, which could be giving the compilation dependent behavior.

C. If your "device" has external pins, try moving the region in the Chip Planner closer to the PIN bank you mapped it to. It will tell you it needs to convert the region to a "fixed" region in order to do this. Once the region is fixed, you will notice that either your design magically works, or the failure is the same between compilations! (A constant failure is better than an intermittent one!!)

D. Try to optimize the placement of the logic, or add additional register-register transfers if there are Pins in different banks. This helps give the signals time to propagate to their destination pin.

To solve my problem I logic-locked each controller independently, ran my Memtest program that I made. My memtest program would compare data read / written and found specific BITS that were failing. I then found the FPGA pin that bit was mapped to, and changed the logic locked region so that it was mapped closer to the failing pin. And magically, everything works!

So now I am running stress tests on the memory, to make sure it is rock solid, while I get ready to add in the rest of my design!

Thanks again.

:D:D:D