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Yes, I do have some very simple logic running at 500 MHz. There is some fmax warnings for that logic, but believe it or not that logic is running just fine.
The difference of SOF/POF seems to exist. I can't believe it either. I have tested this many times, and programming the SOF for the design works fine, no matter how many times I try it... whereas the POF will fail the first time. I understand how FPGAs work (for the most part), and cannot see a probable reason for this.
Thank you very very much for your information. I will give your recommendations a shot.
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Hi,
only one remark to your fmax warnings. Did you run a worst-case and a best case analysis ? The speed difference between slow and fast could be huge. That means when you plan to use the design in production you may run in problems, because the timing of your FPGA's could vary a lot.
Kind regards
GPK
Honored Contributor
