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Hi,
....
Finally, you sat 500MHz, Do you really mean it, don't you have fmax timing problems?
The signaltap may not help in your case so don't read much into it. In fact you better remove it.
sof/pof difference issue is not possible. I believe your design is unstable.
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Yes, I do have some very simple logic running at 500 MHz. There is some fmax warnings for that logic, but believe it or not that logic is running just fine.
The difference of SOF/POF seems to exist. I can't believe it either. I have tested this many times, and programming the SOF for the design works fine, no matter how many times I try it... whereas the POF will fail the first time. I understand how FPGAs work (for the most part), and cannot see a probable reason for this.
Thank you very very much for your information. I will give your recommendations a shot.
Honored Contributor
