Honored Contributor
Honored ContributorI just had an epiphany that I hope could be the issue:
The PCI bus interface is responsible for providing three signals in a clock domain of 33 MHz that is being sourced by the PCI bus. The memory controller looks for when WE goes high, and latches in the data to store to memory immediately, running at 200 MHz(ish.) Its probable that the tpd from the WE and the data/address registers of the PCI bus are different to the memory controller. i.e. if the WE went high, the memory controller, running more than twice as fast as the PCI bus, would grab the data on the data/address lines before they were updated. This would probably cause some of the issues I am encountering. I am testing this theory at the moment, and I hope to have a reason to dance around the room :o.
