Compilation Dependent Behavior

Hi,

Using the PLL depends heavily on Tco being under control, I just wonder how much is your Tco on each of 32 bits outputs to sram.

You will need to know the Tco/Tsu/Th of fpga(configurable) and that of sram.

I am assuming same clk is used for read/write Remember that direction is opposite between read and write.

You can make the assumption that data and clk board delays are equal but finite.

So to optimise the window:

The valid timing window for read is the midpoint of the section of clk period excluding the segment (Tsu + Th of fpga). board delay irrelevant.

The valid timing window for write is the midpoint of the section of clk period excluding the segment (Tsu + Th of sram) but as seen at fpga taking into account the board delay and relative direction of clk/data.

The final optimum point will be that which is average of both cases.

The question is how to force the optimum point:

For read or write you need to control the relation of data to clk by rotating clk.

For read you control the Tsu/Th of fpga + clk phase from PLL.

for write you control Tco of fpga and force it to the required value through same PLL(compromise between the two). Check Tco values are not wandering around.

Finally, you sat 500MHz, Do you really mean it, don't you have fmax timing problems?

The signaltap may not help in your case so don't read much into it. In fact you better remove it.

sof/pof difference issue is not possible. I believe your design is unstable.